SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 72

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.3.6 ASYNCLISTADDR register
[1]
Table 101. PERIODICLISTBASE - Periodic Frame List Base Address register bit description
Address: Value read from func2 of address 10h + 34h
This 32-bit register contains the address of the next asynchronous queue head to be
executed. If the Host Controller is in 64-bit mode—as indicated by logic 1 in 64AC (bit 0 of
the HCCPARAMS register)—the most significant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. Bits 4 to 0 of this register always
return zeros when read. The memory structure referenced by the physical memory pointer
is assumed as 32 B (cache aligned). For bit allocation, see
Table 102. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation
Address: Value read from func2 of address 10h + 38h
[1]
Bit
Symbol
Reset
Access
Bit
31 to 12
11 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
R/W
Symbol
BA[19:0]
reserved
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
7
0
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
6
0
Description
Base Address: These bits correspond to memory address signals
31 to 12, respectively.
-
LPL[3:0]
R/W
R/W
R/W
R/W
R/W
29
21
13
5
0
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
R/W
28
20
12
4
0
0
0
0
4
0
LPL[19:12]
reserved
reserved
LPL[11:4]
R/W
R/W
R/W
R/W
R/W
[1]
[1]
27
19
11
3
0
0
0
0
3
0
Table
R/W
R/W
R/W
R/W
R/W
26
18
10
2
2
0
0
0
0
0
reserved
102.
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
R/W
R/W
[1]
25
17
1
0
0
0
9
0
1
0
R/W
R/W
R/W
R/W
R/W
72 of 97
24
16
0
0
0
0
8
0
0
0