SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 94

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 95. USBSTS - USB Status register bit
Table 96. USBINTR - USB Interrupt Enable register
Table 97. USBINTR - USB Interrupt Enable register
Table 98. FRINDEX - Frame Index register bit
Table 99. FRINDEX - Frame Index register bit
Table 100.PERIODICLISTBASE - Periodic Frame
Table 101.PERIODICLISTBASE - Periodic Frame
Table 102.ASYNCLISTADDR - Current
Table 103.ASYNCLISTADDR - Current
Table 104.CONFIGFLAG - Configure Flag register
Table 105.CONFIGFLAG - Configure Flag register
Table 106.PORTSC 1, 2 - Port Status and Control 1, 2
Table 107.PORTSC 1, 2 - Port Status and Control 1, 2
Table 108.Power consumption . . . . . . . . . . . . . . . . . . . . .78
Table 109.Power consumption: S1 and S3 . . . . . . . . . . . .78
Table 110.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 111.Thermal characteristics . . . . . . . . . . . . . . . . . .79
Table 112.Operating conditions . . . . . . . . . . . . . . . . . . . .79
Table 113.Static characteristics: I
Table 114.Static characteristics: digital pins . . . . . . . . . . .80
Table 115.Static characteristics: PCI interface block . . . .80
Table 116.Static characteristics: USB interface block
Table 117.Dynamic characteristics: system
Table 118.Dynamic characteristics: I
Table 119.Dynamic characteristics: high-speed
Table 120.Dynamic characteristics: full-speed
Table 121.Dynamic characteristics: full-speed
Table 122.PCI clock and IO timing . . . . . . . . . . . . . . . . . .83
Table 123.SnPb eutectic process (from J-STD-020C) . . .87
SAF1562_1
Product data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .69
bit description . . . . . . . . . . . . . . . . . . . . . . . . .69
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
List Base Address register bit allocation . . . . .71
List Base Address register bit description . . . .72
Asynchronous List Address register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Asynchronous List Address register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .73
bit description . . . . . . . . . . . . . . . . . . . . . . . . .73
register bit allocation . . . . . . . . . . . . . . . . . . . .74
register bit description . . . . . . . . . . . . . . . . . . .74
(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .79
(pins DM1 to DM2 and DP1 to DP2) . . . . . . . .80
clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . .81
(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .81
source electrical characteristics . . . . . . . . . . . .82
source electrical characteristics . . . . . . . . . . . .82
source electrical characteristics . . . . . . . . . . . .82
2
C-bus interface
2
C-bus interface
Rev. 01 — 7 February 2007
Table 124.Lead-free process (from J-STD-020C) . . . . . . 87
Table 125.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 126.Revision history . . . . . . . . . . . . . . . . . . . . . . . . 90
Hi-Speed Universal Serial Bus PCI Host Controller
SAF1562
© NXP B.V. 2007. All rights reserved.
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