SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 49

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.15 HcFmRemaining register
[1]
Table 69.
Address: Value read from func0 or func1 of address 10h + 34h
This register is a 14-bit down counter showing the bit time remaining in the current frame.
Table 70
Table 70.
Address: Value read from func0 or func1 of address 10h + 38h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 16
15 and 14 reserved
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
contains the bit allocation of this register.
HcFmInterval - Host Controller Frame Interval register bit description
HcFmRemaining - Host Controller Frame Remaining register bit allocation
Symbol
FIT
FSMPS[14:0] FS Largest Data Packet: This field specifies the value that is loaded
FI[13:0]
R/W
R/W
R/W
R/W
R/W
FRT
23
15
31
23
0
0
7
1
0
0
reserved
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
R/W
[1]
22
14
30
22
0
0
6
1
0
0
Description
Frame Interval Toggle: The HCD toggles this bit whenever it loads a
new value to Frame Interval.
into the largest data packet counter at the beginning of each frame.
The counter value represents the largest amount of data in bits that
can be sent or received by the Host Controller in a single transaction at
any given time, without causing a scheduling overrun. The field value
is calculated by the HCD.
-
Frame Interval: This specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to 11,999. The HCD should
store the current value of this field before resetting the Host Controller
to reset this field to its nominal value. The HCD can then restore the
stored value on completing the reset sequence.
R/W
R/W
R/W
R/W
R/W
21
13
29
21
0
1
5
0
0
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
R/W
20
12
28
20
FSMPS[7:0]
0
0
4
1
0
0
reserved
FI[7:0]
reserved
R/W
R/W
R/W
R/W
R/W
[1]
19
11
27
19
0
1
3
1
0
0
FI[13:8]
[1]
R/W
R/W
R/W
R/W
R/W
18
10
26
18
2
0
1
1
0
0
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
49 of 97
16
24
16
0
8
0
0
1
0
0