MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 114

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Revision History
26 Document Revision History
Table 84
114
Revision
4
3
provides a revision history for this hardware specification.
11/2010 • In
03/2010 • Added
Date
• In
• In
• In
• In
• In
• In
• In
• In
• In
• in
• In
• In
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
to LCRR.
TEST_SEL1 pins—no change in functionality.
Mode Only),” added table footnotes .
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for t
Figure
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
heat spreader.
of open drain type pins.
AVDD_P pins.
Mode,” updated csb_clk frequencies available.
Table
Figure
Section 24.6, “Pull-Up Resistor Requirements,”
Table
Table
Table
Table
Section 10.2, “Local Bus AC Electrical Specifications,”
Table
Table
Figure
Table
Table
24, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted
Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
34, “USB DC Electrical
69, “TePBGA II Pinout Listing,” added Note 17 to eTSEC pins.
74, “CSB Frequency Options for Host Mode,” and
25, “RGMII and RTBI DC Electrical Characteristics,” updated V
40, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for t
69, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
39, “Local Bus General Timing Parameters—PLL Enable Mode,” and
69, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
81, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
22, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and
60, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added
Table 84. Document Revision History
Characteristics,”
Substantive Change(s)
and
removed “Ethernet Management MDIO pin” from list
Table
and in
Table
35, “USB General Timing Parameters (ULPI
Section 22, “Clocking,”
75, “CSB Frequency Options for Agent
IH
min value to 1.7.
LBOTOT1
Freescale Semiconductor
Table
, t
40, “Local Bus
LBOTOT2
updated LCCR
LBKHLR
, t
LBOTOT3
.
.