MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 69

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 46
Figure 47
20 High-Speed Serial Interfaces (HSSI)
The MPC8379E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications. See
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
20.1
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 48
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
Freescale Semiconductor
Note: The clock edge is selectable on SPI.
Note: The clock edge is selectable on SPI.
SPICLK (output)
Signal Terms Definition
shows the SPI timing in slave mode (external clock).
shows the SPI timing in master mode (internal clock).
Output Signals:
shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
Output Signals:
SPICLK (input)
Input Signals:
Input Signals:
(See Note)
(See Note)
(See Note)
(See Note)
SPIMISO
SPIMOSI
SPIMOSI
SPIMISO
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Figure 47. SPI AC Timing in Master Mode (Internal Clock) Diagram
Figure 46. SPI AC Timing in Slave Mode (External Clock) Diagram
t
NEIVKH
Table 1
t
NIIVKH
for the interfaces supported.
t
NIKHOV
t
NIIXKH
t
NEKHOV
tN
EIXKH
High-Speed Serial Interfaces (HSSI)
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