MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 96

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package and Pin Listings
96
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
This output is actively driven during reset rather than being released to high impedance during reset.
These JTAG pins have weak internal pull-up P-FETs that are always enabled.
This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, “MPC837xE Design Checklist,” for more details.
These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
This pin must always be tied to GND using a 0 Ω resistor.
This pin must always be left not connected.
For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR
power using an 18.2 Ω resistor.
This pin must always be tied low. If it is left floating it may cause the device to malfunction.
See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
This pin must not be pulled down during PORESET.
This pin must always be tied to GND.
This pin must always be tied to OVDD.
Open or tie to GND.
Voltage settings are dependent on the frequency used; see
See AN3665, “MPC837xE Design Checklist,” for proper eTSEC termination.
Pull Down
AVDD_C
AVDD_P
AVDD_L
Signal
GVDD
OVDD
NC
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7,
L25, W25, AB26, U27, M28, Y28, G10, A11,
N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5,
A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3,
AC10, AF12, AJ12, K23, Y23, R24, AD24,
Table 69. TePBGA II Pinout Listing (continued)
F16, F17, AD16, AD17
Package Pin Number
AE7, AG7, AD8
B16, AH18
AD13
C11
F13
F12
No Connect
Pull Down
Table
3.
(1.0 V or 1.05 V)
core PLL (1.0 V
Power for eLBC
Power for e300
Power for DDR
other Standard
Voltage (2.5 or
PCI, USB, and
PLL (1.0 V or
system PLL
SDRAM I/O
or 1.05 V)
Pin Type
Power for
1.05 V)
(3.3 V)
1.8 V)
—
—
Power Supply
Freescale Semiconductor
GVDD
OVDD
—
—
—
—
—
Notes
16
16
16
—
—
8
7