MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 78

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces (HSSI)
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 68
78
At recommended operating conditions with XV
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Note:
1
2
3
4
Measurement taken from single ended waveform.
Measurement taken from differential waveform.
Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference
should not exceed 20% of the slowest edge rate. See
SDn_REF_CLK
SDn_REF_CLK
VIH = +200 mV
VIL = –200 mV
describes some AC parameters common to SATA protocols.
Minus
SDn_REF_CLK
SDn_REF_CLK
V
0.0 V
CROSS MEDIAN
Figure 58. Single-Ended Measurement Points for Rise and Fall Time Matching
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
Figure 57. Differential Measurement Points for Rise and Fall Time
Rise Edge Rate
Table 68. SerDes Reference Clock Common AC Parameters
DD_SRDS
or XV
Figure
DD_SRDS
57.
Figure
V
V
Rise-Fall Matching
CROSS MEDIAN
CROSS MEDIAN
= 1.0 V ± 5%.
Rise Edge Rate
Fall Edge Rate
58.
Symbol
V
V
SDn_REF_CLK
SDn_REF_CLK
V
IH
IL
CROSS MEDIAN
+100 mV
–100 mV
Fall Edge Rate
Min
200
1.0
1.0
—
—
T
FALL
–200
Max
4.0
4.0
—
20
T
RISE
Freescale Semiconductor
Unit
V/ns
V/ns
mV
mV
%
Notes
2, 3
2, 3
1, 4
2
2