MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 26

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 8
Figure 9
8.2.2
Table 28
26
At recommended operating conditions with LV
At recommended operating conditions with LV
RX_CLK clock rise time (20%–80%)
RX_CLK clock fall time (80%–20%)
1. The symbols used for timing specifications herein follow the pattern of t
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period
for inputs and t
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for eTSEC.
shows the MII receive AC timing diagram.
presents the RGMII and RTBI AC timing specifications.
RGMII and RTBI AC Timing
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
RXD[3:0]
RX_CLK
RX_ER
RX_DV
Parameter
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Output
Table 27. MII Receive AC Timing Specifications (continued)
Table 28. RGMII and RTBI AC Timing Specifications
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
t
Figure 9. MII Receive AC Timing Diagram
t
MRXH
MRDVKH
DD
DD
of 3.3 V ± 5%.
of 2.5 V ± 5%.
Figure 8. eTSEC AC Test Load
t
MRX
Z
0
MRX
= 50 Ω
Symbol
MRDXKL
t
t
SKRGT
SKRGT
clock reference (K) going to the low (L) state or hold time. Note that, in
t
RGT
Valid Data
Symbol
t
t
MRXR
Specifications
MRXF
1
symbolizes MII receive timing (GR) with respect to the time data
t
MRXF
1
–600
Min
for outputs. For example, t
1.0
7.2
(first two letters of functional block)(signal)(state) (reference)(state)
R
t
Min
MRDXKL
1.0
1.0
t
L
MRXR
= 50 Ω
Typical
8.0
—
0
Typical
LVDD/2
—
—
MRDVKH
Max
600
2.8
8.8
Freescale Semiconductor
Max
4.0
4.0
symbolizes MII
MRX
Unit
clock reference
ps
ns
ns
Notes
Unit
ns
ns
—
2
3