MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 115

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Revision
1
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10/2009 • In
02/2009 • In
12/2008 Initial public release.
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• Updated part numbering information in AF column in
• In
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
800/400 MHz to 4.3 W.
Application at T
at T
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
Specifications,” corrected titles from “Transmitter” to “Receiver”.
to VDD pin.
range to 125–200.
respectively.
rows for SerDes. In addition, changed 666 to 667 MHz.
changed 666 to 667 MHz.
DDR2 SDRAM Output AC Timing Specifications,” and
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist.
footnote 10 and added footnote 15.
addition, modified extended temperature information in notes 1 and 4.
Section 19.2, “SPI AC Timing Specifications,”
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
j
= 65°C (W)”.
13, “DDR2 SDRAM DC Electrical Characteristics for GV
3, “Recommended Operating Conditions,” added “Operating temperature range” values.
5, “MPC8377EMPC8378EMPC8379E Power Dissipation
5, “MPC8377EMPC8378EMPC8379E Power Dissipation
5, “MPC8377EMPC8378EMPC8379E Power Dissipation
11, removed overbar from CFG_CLKIN_DIV.
17, “Current Draw Characteristics for MV
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and
29, “RMII Transmit AC Timing Specifications,” updated t
57, Gen 1i/1.5G Transmitter AC Specifications,” and
69, “TePBGA II Pinout
71, “Operating Frequencies for TePBGA
76, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
77, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
5, “MPC8377EMPC8378EMPC8379E Power Dissipation
21, updated t
69, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
71, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for core_clk.
77, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
82, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
Table 84. Document Revision History (continued)
j
= 65°C (W)”.
DDKHCX
minimum value for 333 MHz to 2.40.
Listing,”
Substantive Change(s)
removed pin THERM0; it is now Reserved. Also added 1.05 V
corrected t
II,”
REF
corrected “DDR2 memory bus frequency (MCK)”
,” updated I
Table
Table
NIKHOX
81, “Part Numbering Nomenclature.” In
69, “TePBGA II Pinout Listing,” added
Table
MVREF
RMTDX
DD
and t
1
1
1
1
,” corrected maximal application for
,” added a column for “Sleep Power
,” added Notes 4 and 5. In addition,
(typ) = 1.8 V,”
,” added a column for “Typical
59, Gen 2i/3G Transmitter AC
I to 2.0 ns.
NEKHOX
maximum value for both DDR1
Document Revision History
Table
to t
Table
NIKHOV
21, “DDR1 and
21, “DDR1 and
and t
NEKHOV
115
,