MPC8379E-RDBA Freescale Semiconductor, MPC8379E-RDBA Datasheet - Page 30

• Manufacturer Part Number: MPC8379E-RDBA
• Description: BOARD REF DESIGN MPC8379E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-RDBA

• Contents: Board
• Memory Type: Flash, SDRAM
• Interface Type: Ethernet, USB, PCI, UART
• Board Size: 170 mm x 170 mm
• Product: Modules
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC83xx
• Silicon Family Name: PowerQUICC II PRO
• Rohs Compliant: Yes
• For Use With/related Products: MPC8379E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 13
Figure 14
8.3
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock).
Figure 15
30
At recommended operating conditions with LV
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Note:
1
The symbols used for timing specifications herein follow the pattern of t
for inputs and t
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
Management Interface Electrical Characteristics
provides the AC test load for eTSEC.
shows the RMII receive AC timing diagram.
provides the AC test load for eTSEC.
(first two letters of functional block)(reference)(state)(signal)(state)
REF_CLK
RXD[1:0]
CRS_DV
RX_ER
Parameter/Condition
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Table 30. RMII Receive AC Timing Specifications (continued)
Output
Output
MRX
Figure 14. RMII Receive AC Timing Diagram
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
t
RMRH
t
DD
RMRDV
of 3.3 V ± 5%.
Figure 13. eTSEC AC Test Load
Figure 15. eTSEC AC Test Load
t
RMR
Z
Z
0
0
MRX
= 50 Ω
= 50 Ω
MRDXKL
clock reference (K) going to the low (L) state or hold time. Note that, in
Valid Data
symbolizes MII receive timing (GR) with respect to the time data
t
RMRF
Symbol
t
t
RMRDX
RMRDV
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
R
R
t
1
RMRDX
t
L
L
RMRR
= 50 Ω
= 50 Ω
Min
4.0
2.0
LVDD/2
LVDD/2
Typical
—
—
MRDVKH
Freescale Semiconductor
symbolizes MII
MRX
Max
—
—
clock reference
Unit
ns
ns