DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 110

KIT DEV ARRIA GX 1AGX60N

DK-DEV-1AGX60N

Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet

Specifications of DK-DEV-1AGX60N

Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372

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2–104
Fast PLL and Channel Layout
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices
Note to
(1) For the number of channels each device supports, refer to
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices
Note to
(1) For the number of channels each device supports, refer to
Arria GX Device Handbook, Volume 1
Figure
Figure
2–81:
2–82:
The receiver and transmitter channels are interleaved as such that each I/O bank on
the left side of the device has one receiver channel and one transmitter channel per
LAB row.
EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices.
fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
4
2
4
2
2
2
2
2
Figure 2–81
4
4
4
4
PLL 1
PLL 2
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
Fast
Fast
LVDS
LVDS
LVDS
LVDS
Clock
Clock
Clock
Clock
shows the fast PLL and channel layout in the EP1AGX20C,
Table
Table 2–30
Clock
Clock
2–30.
Clock
Clock
DPA
DPA
DPA
DPA
through
Table
Quadrant
Quadrant
Quadrant
Quadrant
2–34.
(Note 1)
High-Speed Differential I/O with DPA Support
Quadrant
Quadrant
Quadrant
Quadrant
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Figure 2–82
shows the
(Note 1)

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