DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 13

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
Transceivers
Table 2–3. On-Chip Termination Support by I/O Banks
© December 2009 Altera Corporation
XGMII TXC
0
1
1
1
1
1
1
1
1
00 through FF
07
07
9C
FB
FD
FE
Refer to IEEE 802.3 reserved code
groups
Other value
Transmit State Machine
The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode,
or GIGE mode, depending on the protocol used.
GIGE Mode
In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/,
/Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending
disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set
consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a
negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state
machines do not convert any of the ordered sets to match /C1/ or /C2/, which are
the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/]
and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a
negative-ending disparity after each ordered set.
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the XAUI PCS
code group.
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically
randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/
(/A/) code group is automatically generated between 16 and 31 idle code groups. The
idle randomization on the /A/, /K/, and /R/ code groups is automatically done by
the transmit state machine.
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using
the low-speed parallel clock and clocks out serial data using the high-speed serial
clock from the central or local clock divider blocks. The serializer feeds the data LSB to
MSB to the transmitter output buffer.
XGMII TXD
Table 2–3
lists the code conversion.
Dxx.y
K28.0 or K28.3 or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Refer to IEEE 802.3 reserved code
groups
K30.7
PCS Code-Group
Arria GX Device Handbook, Volume 1
Normal data
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Reserved code groups
Invalid XGMII character
Description
2–7