DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 36

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–30
Figure 2–26. Direct Link Connection
LAB Control Signals
Arria GX Device Handbook, Volume 1
left LAB, TriMatrix
Direct link interconnect from
input/output element (IOE)
block, DSP block, or
Figure 2–26
Each LAB contains dedicated logic for driving control signals to its ALMs. The control
signals include three clocks, three clock enables, two asynchronous clears,
synchronous clear, asynchronous preset or load, and synchronous load control
signals, providing a maximum of 11 control signals at a time. Although synchronous
load and clear signals are generally used when implementing counters, they can also
be used with other functions.
Each LAB can use three clocks and three clock enable signals. However, there can only
be up to two unique clocks per LAB, as shown in the LAB control signal generation
circuit in
example, any ALM in a particular LAB using the labclk1 signal also uses
labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses
two LAB-wide clock signals. De-asserting the clock enable signal turns off the
corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals
and an asynchronous load/preset signal. The asynchronous load acts as a preset
when the asynchronous load data input is tied high. When the asynchronous
load/preset signal is used, the labclkena0 signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide
control signals. The MultiTrack interconnects have inherently low skew. This low
skew allows the MultiTrack interconnects to distribute clock and control signals in
addition to data.
interconnect
Direct link
TM
memory
to left
Figure
Interconnect
shows the direct link connection.
Local
2–27. Each LAB’s clock and clock enable signals are linked. For
LAB
ALMs
Direct link
interconnect
to right
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Logic Array Blocks