DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 59

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–45. M4K RAM Block LAB Row Interface
M-RAM Block
© December 2009 Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
The largest TriMatrix memory block, the M-RAM block, is useful for applications
where a large volume of data must be stored on-chip. Each block contains 589,824
RAM bits (including parity bits). The M-RAM block can be configured in the
following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of a M-RAM block. All
M-RAM block contents power up to an undefined value. Only synchronous operation
is supported in the M-RAM block, so all inputs are registered. Output registers can be
bypassed.
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs
and outputs. Either of the two clocks feeding the block can clock M-RAM block
registers (renwe, address, byte enable, datain, and output registers). You can
bypass the output register. The six labclk signals or local interconnect can drive the
control signals for the A and B ports of the M-RAM block. ALMs can also control the
clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
M4K RAM Block Local
Interconnect Region
16
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
Figure
dataout
byte
enable
36
2–46.
6
Arria GX Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
2–53