DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 90

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–84
Figure 2–69. Column I/O Block Connection to the Interconnect
Note to
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and
Arria GX Device Handbook, Volume 1
io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables
io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four
synchronous clear and preset signals
Figure
2–69:
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
Figure 2–69
There are 32 control and data signals that feed each row or column I/O block. These
control and data signals are driven from the logic array. The row or column IOE
clocks, io_clk[7..0], provide a dedicated routing resource for low-skew,
high-speed clocks. I/O clocks are generated from global or regional clocks (refer to
“PLLs and Clock Networks” on page
I/O Block
32 Data &
Interconnect
LAB
LAB Local
io_sclr/spreset[3..0]
shows how a column I/O block connects to the logic array.
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
.
2–66).
IO_dataina[3..0]
IO_datainb[3..0]
LAB
© December 2009 Altera Corporation
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
Chapter 2: Arria GX Architecture
I/O Structure