DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 65
DK-DEV-1AGX60N
Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of DK-DEV-1AGX60N
Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372
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Chapter 2: Arria GX Architecture
Digital Signal Processing Block
© December 2009 Altera Corporation
As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a
single DSP block and is true for any combination of signed, unsigned, or mixed sign
multiplications.
Figure 2–50
Figure 2–50. DSP Blocks Arranged in Columns
Table 2–13
multipliers can optionally feed an adder/subtractor or accumulator in the block
depending on the configuration, which makes routing to ALMs easier, saves ALM
routing resources, and increases performance because all connections and blocks are
in the DSP block.
lists the number of DSP blocks in each Arria GX device. DSP block
shows one of the columns with surrounding LAB rows.
4 LAB
Rows
DSP Block
DSP Block
Column
Arria GX Device Handbook, Volume 1
2–59
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