DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 48

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–42
Register Chain
Arria GX Device Handbook, Volume 1
chains are also top- or bottom-half bypassable. This capability allows the shared
arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other
half available for narrower fan-in functionality. Every other LAB column is top-half
bypassable, while the other LAB columns are bottom-half bypassable. For more
information about shared arithmetic chain interconnect, refer to
Interconnect” on page
In addition to the general routing outputs, the ALMs in a LAB have register chain
outputs. Register chain routing allows registers in the same LAB to be cascaded
together. The register chain interconnect allows a LAB to use LUTs for a single
combinational function and the registers to be used for an unrelated shift register
implementation. These resources speed up connections between ALMs while saving
local interconnect resources (refer to
automatically takes advantage of these resources to improve utilization and
performance. For more information about register chain interconnect, refer to
“MultiTrack Interconnect” on page
2–44.
2–44.
Figure
2–38). The Quartus II Compiler
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
“MultiTrack
Adaptive Logic Modules