DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 23
![KIT DEV ARRIA GX 1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_sml.jpg)
DK-DEV-1AGX60N
Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of DK-DEV-1AGX60N
Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372
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Chapter 2: Arria GX Architecture
Transceivers
Figure 2–16. Before and After the Channel Aligner
© December 2009 Altera Corporation
Figure 2–16
channels after the channel aligner.
Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clock sources. Frequency differences in the order of a few
hundred PPM can potentially corrupt the data at the receiver.
The rate matcher compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if
the local receiver is running a faster clock than the upstream transmitter. It deletes a
skip character if the local receiver is running a slower clock than the upstream
transmitter. The Quartus II software automatically configures the appropriate skip
character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base
Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial
RapidIO and must be implemented in the PLD logic array or external circuits
depending on your system design.
Table 2–5
XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance
Lane 3
Lane 3
Lane 2
Lane 1
Lane 0
PCI Express (PIPE)
Function Mode
lists the maximum frequency difference that the rate matcher can tolerate in
Lane 1
shows misaligned channels before the channel aligner and the aligned
Lane 0
Basic
XAUI
GIGE
Lane 2
K
K
K
K
K
K
K
K
K
K
K
K
K
K
R
R
R
R
R
K
R
K
A
A
A
A
A
R
A
R
K
K
K
K
K
A
K
A
R
R
R
R
R
K
R
K
R
R
R
R
R
R
R
R
K
K
K
K
K
R
K
R
± 100
± 300
± 100
± 300
K
K
K
K
K
PPM
K
K
K
R
R
R
R
R
K
R
K
K
K
K
K
K
R
Arria GX Device Handbook, Volume 1
K
R
R
R
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K
R
K
R
R
2–17
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