DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 52

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–46
Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Arria GX Device Handbook, Volume 1
C4 interconnects span four LABs, M512, or M4K blocks up or down from a source
LAB. Every LAB has its own set of C4 interconnects to drive either up or down.
Figure 2–41
interconnects can drive and be driven by all types of architecture blocks, including
DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB
interconnection, a primary LAB or its LAB neighbor can drive a given C4
interconnect. C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
Routing to Adjacent ALM
Carry Chain & Shared
shows the C4 interconnect connections from a LAB in a column. C4
Arithmetic Chain
Interconnect
Local
Local Interconnect
Routing Among ALMs
in the LAB
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
Register Chain
Routing to Adjacent
ALM's Register Input
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect