UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 115

8BIT UC, 32K FLASH, 1KB RAM, LCD

UPD78F0413GA-GAM-AX

Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0413GA-GAM-AX

Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal

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(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFA1H
Symbol
MCM
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
XSEL
MCS
7
0
0
0
1
1
0
1
After reset: 00H
2. A clock other than f
Figure 5-6. Format of Main Clock Mode Register (MCM)
Operates with internal high-speed oscillation clock
Operates with high-speed system clock
regardless of the setting of XSEL and MCM0.
MCM0
When “f
Watchdog timer (operates with internal low-speed oscillation clock)
When “f
(operates with internal low-speed oscillation clock)
(operates with internal low-speed oscillation clock)
Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM00 is selected (TI000 pin valid
edge))
6
0
0
1
0
1
R/W
CHAPTER 5 CLOCK GENERATOR
Internal high-speed oscillation clock
(f
High-speed system clock (f
RL
RH
RL
”, “f
Selection of clock supplied to main system clock and peripheral hardware
)
/2
Note
User’s Manual U18698EJ1V0UD
5
0
3
” is selected as the LCD source clock for LCD controller/driver
RL
Main system clock (f
/2
7
”, or “f
PRS
4
0
Main system clock status
RL
is supplied to the following peripheral functions
/2
9
” is selected as the count clock for 8-bit timer H1
XH
XP
)
)
3
0
Internal high-speed oscillation clock
(f
High-speed system clock (f
RH
XSEL
Peripheral hardware clock (f
)
<2>
MCS
<1>
XH
)
MCM0
<0>
PRS
)
115

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