UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 330

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

13.4.3 Dedicated baud rate generator
generates a serial clock for transmission/reception of UART0.
(1) Configuration of baud rate generator
330
The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and
Separate 5-bit counters are provided for transmission and reception.
Base clock
The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is
supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0
(ASIM0) is 1. This clock is called the base clock and its frequency is called f
to low level when POWER0 = 0.
Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when POWER0 = 1 and TXE0 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).
Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
event counter
8-bit timer/
50 output
f
TXE0:
RXE0:
BRGC0:
f
PRS
PRS
f
PRS
/2
/2
/2
5
3
BRGC0: TPS01, TPS00
Figure 13-12. Configuration of Baud Rate Generator
Bit 6 of ASIM0
Bit 5 of ASIM0
Baud rate generator control register 0
POWER0
Selector
CHAPTER 13 SERIAL INTERFACE UART0
User’s Manual U18698EJ1V0UD
f
XCLK0
POWER0, TXE0 (or RXE0)
BRGC0: MDL04 to MDL00
Match detector
5-bit counter
Baud rate generator
1/2
XCLK0
. The base clock is fixed
Baud rate