UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 461

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
Remark f
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event counter 00
8-bit timer/event
counter
8-bit timer
Real-time counter
Watchdog timer
Buzzer output
10-bit successive approximation
type A/D converter
Serial interface
LCD controller/driver
Manchester code generator
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
RL
2.
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
f
f
f
f
RH
X
EXCLK
XT
RL
PD78F041x only.
:
HALT Mode Setting
:
:
:
:
Note 2
UART0
UART6
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
f
f
f
f
RH
X
EXCLK
XT
50
51
52
H0
H1
H2
Note 1
Note 1
Table 19-1. Operating Statuses in HALT Mode (2/2)
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Status before HALT mode was set is retained
Operation stopped
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable. However, operation disabled when peripheral hardware clock (f
Operable
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
CHAPTER 19 STANDBY FUNCTION
User’s Manual U18698EJ1V0UD
When CPU Is Operating on XT1 Clock (f
XT
)
PRS
) is stopped.
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