UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 533

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
OR
XOR
CMP
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 26 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U18698EJ1V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
8
5
9
5
9
9
9
8
5
9
5
9
9
9
8
5
9
5
9
9
9
A
(saddr)
A
r
A
A
A
A
A
A
A
(saddr)
A
r
A
A
A
A
A
A
A
(saddr)
A
r
A
A
A
A
A
A
A
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
r
r
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
(saddr)
(saddr)
CPU
) selected by the processor clock
Operation
byte
byte
Z AC CY
Flag
533