UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 132

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

132
(1) Example of setting procedure when oscillating the XT1 clock
(2) Example of setting procedure when using the subsystem clock as the CPU clock
(3) Example of setting procedure when stopping the subsystem clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
<2> Waiting for the stabilization of the subsystem clock oscillation
Caution Do not change the value of OSCSELS while the subsystem clock is operating.
<1> Setting subsystem clock oscillation
<2> Switching the CPU clock (PCC register)
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the subsystem clock (OSCCTL register)
Cautions 1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When OSCSELS is set as any of the following, the mode is switched from port mode to XT1 oscillation
mode.
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
(See 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
When CSS is set to 1, the subsystem clock is supplied to the CPU.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
When OSCSELS is cleared to 0, XT1 oscillation is stopped.
OSCSELS
CSS
CLS
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
0
0
1
1
1
peripheral hardware if it is operating on the subsystem clock.
XT1 oscillation mode
Operation Mode of Subsystem
PCC2
MCS
0
1
0
0
0
0
1
Other than above
Clock Pin
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
PCC1
CHAPTER 5 CLOCK GENERATOR
0
0
1
1
0
User’s Manual U18698EJ1V0UD
Note
PCC0
0
1
0
1
0
Crystal/ceramic resonator connection
f
Setting prohibited
SUB
P123/XT1 Pin
CPU Clock Status
/2
CPU Clock (f
CPU
) Selection
P124/XT2 Pin