UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 282
UPD78F0413GA-GAM-AX
Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet
1.UPD78F0413GA-GAM-AX.pdf
(562 pages)
Specifications of UPD78F0413GA-GAM-AX
Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal
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10.3 Register Controlling Watchdog Timer
282
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AH
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
Address: FF99H
Symbol
WDTE
operate watchdog timer, set WDTON to 1.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
0 (watchdog timer count operation disabled)
1 (watchdog timer count operation enabled)
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes operation.
7
Figure 10-2. Format of Watchdog Timer Enable Register (WDTE)
After reset: 9AH/1AH
WDTON Setting Value
6
CHAPTER 10 WATCHDOG TIMER
Note
5
User’s Manual U18698EJ1V0UD
R/W
4
Note
1AH
9AH
.
3
WDTE Reset Value
2
1
0
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