UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 168

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input
start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the
timer/event counter, TM00 starts counting up. When the valid edge of the TI000 pin is detected during the counting
operation, TM00 is cleared to 0000H and starts counting up again. If the valid edge of the TI000 pin is not detected,
TM00 overflows and continues counting.
the start of the operation.
(1) Operation in clear & start mode entered by TI000 pin valid edge input
168
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear &
The valid edge of the TI000 pin is a cause to clear TM00. Starting the counter is not controlled immediately after
CR000 and CR010 are used as compare registers and capture registers.
Remarks 1. For the setting of the I/O pins, see 6.3 (6) Port mode register 3 (PM3).
(a) When CR000 and CR010 are used as compare registers
(b) When CR000 and CR010 are used as capture registers
Caution Do not set the count clock as the valid edge of the TI000 pin (PRM002, PRM001, and PRM000 =
(CR000: compare register, CR010: compare register)
Signals INTTM000 and INTTM010 are generated when the value of TM00 matches the value of CR000 and
CR010.
The count value of TM00 is captured to CR000 and the INTTM000 signal is generated when the valid edge is
input to the TI010 pin (or when the phase reverse to that of the valid edge is input to the TI000 pin).
When the valid edge is input to the TI000 pin, the count value of TM00 is captured to CR010 and the
INTTM010 signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Figure 6-23. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
Count clock
TI000 pin
110). When PRM002, PRM001, and PRM000 = 110, TM00 is cleared.
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
TMC003, TMC002
Operable bits
(CR000: Compare Register, CR010: Compare Register)
detection
Edge
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U18698EJ1V0UD
Compare register
Timer counter
Match signal
(CR010)
(TM00)
Compare register
Clear
(CR000)
Match signal
controller
Output
TO00
output
Interrupt signal
(INTTM000)
Interrupt signal
(INTTM010)
TO00 pin