XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 126

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
FIFO Latency Register (FIFOLR) (Indirect Address = 0xn0H, 0x17H)
B
B
IT
IT
B
N
R/W
N
1-0
7-5
4-0
IT
UMBER
0
UMBER
7
Slip Buffer Enable
Reserved
FIFO Latency
Reserved
B
R/W
IT
0
6
B
B
IT
IT
N
N
AME
AME
B
R/W
IT
0
5
B
B
IT
IT
R/W
R/W
R/W
T
T
YPE
YPE
B
R/W
IT
0
4
Slip Buffer Enable:
When these bits are set to 00:
Slip Buffer is bypassed. The Receive Payload Data is passing
from the Receive Framer Module to the Receive Payload Data
Output Interface directly without routing through the Slip Buffer.
The Receive Serial Clock signal (RxSerClk_n) is an output.
When these bits are set to 01:
The Elastic Store (Slip Buffer) is enabled. The Receive Payload
Data is passing from the Receive Framer Module through the
Slip Buffer to the Receive Payload Data Output Interface. The
Receive Serial Clock signal (RxSerClk_n) is an input.
When these bits are set to 10:
The Slip Buffer acts as a FIFO. The FIFO Latency Register
(FLR) determines the data latency. The Receive Payload Data
is passing from the Receive Framer Module through the FIFO to
the Receive Payload Data Output Interface. The Receive Serial
Clock signal (RxSerClk_n) is an input.
When these bits are set to 11:
Slip Buffer is bypassed. The Receive Payload Data is passing
from the Receive Framer Module to the Receive Payload Data
Output Interface directly without routing through the Slip Buffer.
The Receive Serial Clock signal (RxSerClk_n) is an output.
FIFO Latency:
These bits determine depth of the FIFO in terms of bytes. The
largest possible value is thirty-two bytes or one E1 frame.
106
B
R/W
IT
0
3
FIFO Latency [4:0]
B
B
B
R/W
IT
IT
IT
0
D
D
2
ESCRIPTION
ESCRIPTION
B
R/W
IT
0
1
REV. 1.0.1
B
R/W
IT
0
0