XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 64

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The procedure that the µC/µP must use to perform the remaining read cycles, within this Burst Access
operation, is presented below.
For subsequent read operations, within this burst cycle, the µC/µP simply repeats steps 1 through 3, as
illustrated in
In addition to the behavior of the Microprocessor Interface signals,
regarding the Burst Access Operation.
F
b. The Framer performs this address incrementing process even though there are no changes in the Address
a. The Framer internally increments the address value, from the original latched value shown in
1.3.2.3.1.1.2
IGURE
B.0
B.1
B.2
B.3
B.4
b.
a.
This is illustrated by the data, appearing on the data bus, (for the first read access) being labeled Valid
Data at Offset = 0x01 and that for the second read access being labeled Valid Data at Offset = 0x02.
Bus Data, A[6:0].
The Framer will internally increments the latched address value (within the Microprocessor Interface circuitry).
The output drivers of the bi-directional data bus, D[7:0] are enabled. At some time later, the register or buffer location
corresponding to the incremented latched address value will be driven onto the bi-directional data bus.
9. I
Execute each subsequent Read Cycles, as described in steps 1 through 3 below.
Without toggling the ALE_AS input pin (e.g., keeping it "Low"), toggle the RD_DS input pin "Low". This
step accomplishes the following.
Immediately after the Read Strobe pin toggles "Low" the Framer will toggle the RDY_DTACK (READY)
output pin "Low" to indicate its NOT READY status.
After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data is ready to be read by toggling the RDY_DTACK
(READY) signal "High".
After the µC/µP detects the RDY_DTACK signal (from the Framer), it can terminate the Read cycle by
toggling the RD_DS (Read Strobe) input pin "High".
RDY_DTACK
NTEL
Figure 9
ALE_AS
A[6:0]
D[7:0]
µP I
WR
RD
CS
NTERFACE
.
Subsequent Read Operations
S
Valid
IGNALS
Not
,
DURING SUBSEQUENT
Offset = 0x01
Valid Data at
Address of Initial Target Register (Offset = 0x00)
44
R
EAD
Valid
O
Not
PERATIONS OF A
Figure 9
Offset = 0x02
Valid Data at
also illustrates other points
B
URST
I/O C
Figure 8
YCLE
REV. 1.0.1
.