XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 62

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
If the XRT84L38 Framer is interfaced to an Intel-type µC/µP (e.g., the 80x86 family, etc.), then it should be
configured to operate in the Intel mode (by tying the MOTO pin to ground). Intel-type Read and Write Burst I/O
Access operations are described below.
When an Intel-type µC/µP wants to read the contents of numerous registers or buffer locations over a
contiguous range of addresses, then it should do the following.
Each of these operations within the burst access are described below.
The initial read operation of an Intel-type read burst access is accomplished by executing a Programmed I/O
Read Cycle as summarized below.
N
b. Perform the remaining read operations of the burst access.
a. Perform the initial read operation of the burst access.
c. Terminate the burst access operation.
1.3.2.3.1.1
1.3.2.3.1.1.1
OTE
A.0
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
: The ALE_AS input pin should remain "Low" for the remainder of this Burst Access operation.
Execute a Single Ordinary (Programmed I/O) Read Cycle, as described in steps A.1 through A.7
below.
Place the address of the initial-target register or buffer location (within the Framer) on the Address Bus
input pins A[6:0].
While the µC/µP is placing this address value onto the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS input pin of the Framer, by toggling it "Low". This step
enables further communication between the µC/µP and the Framer Microprocessor Interface block.
Assert the ALE_AS (Address Latch Enable) pin by toggling it "High". This step enables the Address
Bus input drivers, within the Microprocessor Interface block of the Framer.
After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Data
Setup time), the µC/µP should then toggle the ALE_AS pin "Low". This step latches the contents, on
the Address Bus pins, A[6:0], into the Framer Microprocessor Interface block. At this point, the initial
address of the burst access has now been selected.
Next, the µC/µP should indicate that this current bus cycle is a Read Operation by toggling the RD_DS
(Read Strobe) input pin "Low". This action also enables the bi-directional data bus output drivers of the
Framer. At this point, the bi-directional data bus output drivers will proceed to drive the contents of the
addressed register onto the bi-directional data bus, D[7:0].
Immediately after the µC/µP toggles the Read Strobe signal "Low", the Framer will toggle the
RDY_DTACK (READY) output pin "Low". The Framer does this in order to inform the µC/µP that the
data (to be read from the data bus) is NOT READY to be latched into the µC/µP.
After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data is ready to be read, by toggling the RDY_DTACK
(Ready) signal "High".
After the µC/µP detects the RDY_DTACK signal (from the Framer), it can then will terminate the Read
cycle by toggling the RD_DS (Read Strobe) input pin "High".
Intel-Mode Read Burst Access
Initial Read Operation: Intel mode
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REV. 1.0.1