XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 56

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
1.3
T
RDY_DTAC
RDY_DTAC
ABLE
XRT84L38
XRT84L38
P
P
ALE_AS
ALE_AS
P
IN
IN
IN
A[6:0]
WR
WR
RD
RD
K
K
N
N
CS
N
5: XRT84L38 M
AME
AME
Interfacing the XRT84L38 to the Local µC/µP via the Microprocessor Interface Block
AME
E
E
QUIVALENT
QUIVALENT
M
READY*
DTACK*
OTOROLA
T
I
R/W*
YPE
WR*
ALE
RD*
NTEL
AS*
DS*
I
I
T
ABLE
ICROPROCESSOR
T
Seven-Bit Address Bus Inputs
The XRT84L38 Framer Microprocessor Interface uses a Multiplexed Address bus. This
address bus is provided to permit the user to select an on-chip register or buffer location for
Read/Write access.
Chip Select Input
This active-low signal selects the Microprocessor Interface of the XRT84L38 Framer and
enables Read/Write operations with the on-chip registers/buffer locations.
P
P
ABLE
IN
IN
7: M
T
T
YPE
YPE
6: I
O
O
I
I
I
I
I
I
OTOROLA
NTEL MODE
Address-Latch Enable: This active-high signal is used to latch the contents on
the address bus, A[6:0]. The contents of the Address Bus are latched into the
A[6:0] inputs on the falling edge of ALE_AS. Additionally, this signal can be
used to indicate the start of a burst cycle.
Read Signal: This active-low input functions as the read signal from the local
When this signal goes "Low", the Framer Microprocessor Interface places the
contents of the addressed register on the Data Bus pins, D[7:0]. The Data Bus is
tri-stated once this input signal returns "High".
Write Signal: This active-low input functions as the write signal from the local
µP
via A[6:0], on the rising edge of this signal.
Ready Output: This active-low signal is provided by the Framer and indicates
that the current read or write cycle is to be extended until this signal is asserted.
The local
toggles "Low" when the device is ready for the next Read or Write cycle.
Address Strobe: This active-low signal is used to latch the contents on the
address bus input pins, A[6:0], into the Microprocessor Interface circuitry. The
contents of the Address Bus are latched into the Framer on the rising edge of the
ALE_AS signal. This signal can also be used to indicate the start of a burst cycle.
Data Strobe: This signal latches the contents of the bi-directional data bus pins
into the Addressed Register within the Framer during a Write Cycle.
Read/Write Input: When this pin is "High", it indicates a Read Cycle. When this
pin is "Low", it indicates a Write cycle.
Data Transfer Acknowledge: The Framer asserts DTACK in order to inform the
CPU that the present READ or WRITE cycle is nearly complete. The 68000 fam-
ily of CPUs requires this signal from its peripheral devices in order to quickly and
properly complete a READ or WRITE cycle.
. The contents of the Data Bus (D[7:0]) is written into the addressed register
I
NTERFACE
M
AND
ODE
: M
µP
M
: M
ICROPROCESSOR
typically inserts WAIT states until this signal is asserted. This output
OTOROLA
S
ICROPROCESSOR
IGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE
36
M
ODES
D
ESCRIPTION
I
NTERFACE
D
D
I
ESCRIPTION
ESCRIPTION
NTERFACE
S
IGNALS
S
IGNALS
REV. 1.0.1
I
NTEL
µP
.