XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 298

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The Receive Time-slot Indication Bits (RxTSb[4:0]_n) are multiplexed I/O pins. The functionality of these pins
is governed by the value of Receive Fractional E1 Output Enable bit of the Receive Interface Control Register
(RICR). The following table illustrates the configurations of the Receive Fractional E1 Input Enable bit.
RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H)
When configured to operate in normal condition (that is, when the Receive Fractional E1 Input Enable bit is
equal to zero), these bits reflect the five-bit binary value of the Time Slot number (0-31) being outputted and
processed by the Receive Payload Data Output Interface block of the framer. RxTSb[4] represents the MSB of
the binary value and RxTSb[0] represents the LSB.
When the Receive Fractional E1 Output Enable bit is equal to one, the RxTSb[0]_n bit becomes the Receive
Fractional E1 Output signal (RxFrTD_n). This output pin carries Fractional E1 Output data extracted by the
framer from the incoming E1 data stream. The Fractional E1 Output Interface allows certain time-slots of E1
data to be routed to destinations other than the local Terminal Equipment. Function of the Fractional E1 Output
signal will be discussed in details in later sections.
When the Receive Fractional E1 Output Enable bit is equal to one, the RxTSb[1]_n bit becomes the Receive
Signaling Data Output signal (RxSig_n). These output pins can be used to carry robbed-bit signaling data
extracted from the inbound E1 frame. Function of the Receive Signaling Data Output signal will be discussed in
details in later sections.
When the Receive Fractional E1 Output Enable bit is equal to one, the RxTSb[2]_n bit serially outputs all five-
bit binary values of the Time Slot number (0-31) being outputted and processed by the Receive Payload Data
Output Interface block of the framer. MSB of the binary value is presented first and the LSB is presented last.
The RxTSb[3]_n and RxTSb[4}_n pins are not multiplexed.
The table below shows functionality of the RxTSb[2:0] bits when the Receive Fractional E1 Output bit is set to
different values.
N
UMBER
B
4
IT
R
RxTSb[0]
ECEIVE
Output Enable
Fractional E1
B
Receive
IT
F
N
RACTIONAL
AME
B
E1 O
IT
R/W
T
YPE
UTPUT
0 - The Receive Time-slot Indication bits (RxTSb[4:0] are outputting five-bit
binary values of Time-slot number (0-31) being accepted and processed by the
Receive Payload Data Output Interface block of the framer.
The Receive Time-slot Indicator Clock signal (RxTSClk_n) is a 256KHz clock
that pulses HIGH for one E1 bit period whenever the Receive Payload Data Out-
put Interface block is accepting the LSB of each of the twenty-four time slots.
1 - The RxTSb[0]_n bit becomes the Receive Fractional E1 Output signal
(RxFrTD_n) which carries Fractional E1 payload data from the framer.
The RxTSb[1]_n bit becomes the Receive Signaling Data Output signal
(RxSig_n) which is used to carry robbed-bit signaling data extracted from the
inbound E1 frame.
The RxTSb[2]_n bit serially outputs all five-bit binary values of the Time Slot
number (0-31) being accepted and processed by the Receive Payload Data Out-
put Interface block of the framer.
The RxTSClk_n will output gaped fractional E1 clock that can be used by Termi-
nal Equipment to latch in Fractional E1 payload data at rising edge of the clock.
Or,
The RxTSClk_n pin will be a clock enable signal to Receive Fractional E1 Output
signal (RxFrTD_n) when the un-gaped Receive Serail Output Clock
(RxSerClk_n) is used to latch in Fractional E1 Payload Data into the Terminal
Equipment.
Output
B
IT
= 0
278
R
RxFrTD
ECEIVE
B
IT
D
ESCRIPTION
F
RACTIONAL
E1 O
UTPUT
Output
B
IT
= 1
REV. 1.0.1