XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 151
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REV. 1.0.1
B
IT
N
3-0
UMBER
Receive Conditioning
Select
B
IT
N
AME
B
IT
R/W
T
YPE
Receive Conditioning Select:
When these bits are set to 0000:
The received DS1 payload data of this DS0 channel is
unchanged.
When these bits are set to 0001:
All 8 bits of the input DS1 payload data of this DS0 channel are
inverted.
When these bits are set to 0010:
The even bits of the input DS1 payload data of this DS0 channel
are inverted.
When these bits are set to 0011:
The odd bits of the input DS1 payload data of this DS0 channel
are inverted.
When these bits are set to 0100:
The input DS1 payload data of this DS0 channel are replaced by
the octet stored in User IDLE Code Register (UCR).
When these bits are set to 0101:
The input DS1 payload data of this DS0 channel are replaced by
BUSY code (0x7F).
When these bits are set to 0110:
The input DS1 payload data of this DS0 channel are replaced by
VACANT code (0xFF).
When these bits are set to 0111:
The input DS1 payload data of this DS0 channel are replaced by
BUSY_TS code (111xxxxx).
When these bits are set to 1000:
The input DS1 payload data of this DS0 channel are replaced by
MUX-Out-Of-Frame (MOOF) code with value 0x1A.
When these bits are set to 1001:
The input DS1 payload data of this DS0 channel are replaced by
the A-law digital milliwatt pattern.
When these bits are set to 1010:
The input DS1 payload data of this DS0 channel are replaced by
the u-law digital milliwatt pattern.
When these bits are set to 1011:
The MSB bit of the input DS1 payload data of this DS0 channel
is inverted.
When these bits are set to 1100:
All bits of the input DS1 payload data of this DS0 channel except
MSB bit are inverted.
When these bits are set to 1101:
The input DS1 payload data of this DS0 channel are replaced by
PRBS pattern created by the internal PRBS Generator of
XRT84L38 framer.
When these bits are set to 1110:
The input DS1 payload data of this DS0 channel is unchanged.
When these bits are set to 1111:
This channel is configured as D or E timeslot.
131
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38
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