XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 58

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Figure 4
during an Intel-type Programmed I/O Read Operation.
Whenever an Intel-type µC/µP wishes to write a byte or word of data into a register or buffer location, within the
Framer, it should do the following.
F
2. While the µC/µP is placing this address value on the Address Bus, the Address Decoding circuitry within
3. Toggle the ALE_AS (Address Latch Enable) input pin "High". This step enables the Address Bus input driv-
4. After allowing the data on the Address Bus pins to settle, by waiting the appropriate Address Data Setup
5. Next, the µC/µP should indicate that this current bus cycle is a Read Operation by toggling the RD_DS
6. Immediately after the µC/µP toggles the Read Strobe signal "Low", the Framer toggles the RDY_DTACK
7. After some settling time, the data on the bi-directional data bus stabilizes and can be read by the µC/µP.
8. After the µC/µP detects the RDY_DTACK signal, from the Framer, it can terminate the Read Cycle by tog-
1. Assert the ALE_AS (Address Latch Enable) input pin by toggling it "High". When the µC/µP asserts the
2. Place the address of the target register or buffer location, within the Framer, on the Address Bus input pins,
3. While the µC/µP is placing this address value onto the Address Bus, the Address Decoding circuitry within
1.3.2.2.1.2
IGURE
the user's system should assert the CS (Chip Select) pin of the Framer, by toggling it "Low". This action
enables further communication between the µC/µP and the Framer Microprocessor Interface block.
ers, within the Microprocessor Interface block of the Framer.
time, the µC/µP should toggle the ALE_AS pin "Low". This step causes the Framer to latch the contents of
the Address Bus into its internal circuitry. At this point, the address of the register or buffer locations, within
the Framer, has been selected.
(Read Strobe) input pin "Low". This action also enables the bi-directional data bus output drivers of the
Framer. At this point, the bi-directional data bus output drivers proceeds to drive the contents of the latched
addressed register, or buffer location, onto the bi-directional data bus, D[7:0].
output pin "Low". The Framer does this in order to inform the µC/µP that the data to be read from the data
bus is NOT READY to be latched into the µC/µP.
The Framer indicates that this data can be read by toggling the RDY_DTACK (READY) signal "High".
gling the RD_DS (Read Strobe) input pin "High".
ALE_AS input pin, it enables the Address Bus Input Drivers within the Framer chip.
A[6:0].
the user's system should assert the CS input pin of the Framer by toggling it "Low". This step enables fur-
ther communication between the µC/µP and the Framer Microprocessor Interface block.
4. I
RDY_DTACK
presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals
NTEL
WR_R/W
ALE_AS
A[6:0]
D[7:0]
µP I
RD
CS
The Intel Mode Write Cycle
NTERFACE SIGNALS DURING
P
ROGRAMMED
Address of target Register
38
Not Valid
I/O R
EAD
O
Valid
PERATION
REV. 1.0.1