XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 132

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
B
IT
N
UMBER
7
6
5
Receive Fraction Data
Interface Select
Reserved
Receive Payload Clock
Select / Receive Sync-
Pulse Low Active Select
B
IT
N
AME
B
IT
R/W
R/W
T
YPE
Receive Fraction Data Interface Select:
When this bit is set to 0:
The Receive Serial Fractional Data (RxFrTD_n) output pins are
used to output fractional serial data.
The Receive Timeslot Clock (RxTsClk_n) pins are used to output
fractional data clock.
When this bit is set to 1:
The Receive Timeslot Clock (RxTSClk_n) pins are used to out-
put fractional serial data enable signal.
Fractional serial data is clocked out from the framer using
ungapped RxSerClk_n signals.
Receive Payload Clock Select / Receive Sync- Pulse Low
Active Select:
When this bit is set to 0:
The RxSerClk_n pins will output ungapped Receive clock for
correspondent DS1/E1 clock rates.
In non-1.544 MHz mode for DS1 or non-2.048 MHz mode for E1,
the XRT84L38 chip generates a HIGH active pulse for frame
synchronization.
When this bit is set to 1:
The RxSerClk_n pins will output a gapped Receive clock with
OH bit period blocked for correspondent DS1/E1 clock rates.
In non-1.544 MHz mode for DS1 or non-2.048 MHz mode for E1,
the XRT84L38 chip generates a LOW active pulse for frame syn-
chronization.
112
B
IT
D
ESCRIPTION
REV. 1.0.1