XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 71
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REV. 1.0.1
Figure 14
during the Initial write operation within a Burst Access, for a Motorola-type µC/µP.
At the completion of this initial write cycle, the µC/µP has written a byte or word into the first register or buffer
location (within the Framer) for this particular burst I/O access. In order to illustrate how this burst I/O cycle
works, the byte (or word) of data, that is being written in
= 0x00).
The procedure that the µC/µP must use to perform the remaining write cycles, within this burst access
operation, is presented below.
F
b. It causes the Framer to internally increment the value of the latched address.
a. It enables the input drivers of the bi-directional data bus.
1.3.2.3.2.2.2
IGURE
B.0
B.1
B.2
B.3
14. M
Execute each subsequent write cycle, as described in steps B.1 through B.3.
Without toggling the ALE_AS input pin (e.g., keeping it "Low"), apply the value of the next byte or word
(to be written into the Framer) to the bi-directional data bus pins, D[7:0].
Toggle the
After waiting the appropriate amount of settling time the data, in the internal data bus, will stabilize and
is ready to be latched into the Framer Microprocessor Interface block. At this point, the µC/µP should
latch the data into the Framer by toggling the
RDY_DTACK
presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
ALE_AS
A[6:0]
D[7:0]
OTOROLA
WR
RD
CS
WR_R/W
The Subsequent Write Operations
µP I
NTERFACE SIGNALS
(Write Strobe) input pin "Low". This step accomplishes two things.
Address of Initial Target Register (Offset = 0x00)
,
DURING THE
Data to be Written
WR_R/W
(Offset = 0x00)
51
Figure 14
I
NITIAL
input pin "High".
has been labeled Data to be Written (Offset
W
RITE
O
PERATION OF A
OCTAL T1/E1/J1 FRAMER
B
URST
XRT84L38
C
YCLE
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