XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 74

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
To access each individual register inside each group, a two-step access by the micro-controller to the
XRT84L38 is required. In the first step, a micro-controller WRITE access specifying the indirect address for
that register within the register group should be done to the indirect address register of that group. In the
second step, a micro-controller READ or WRITE should access the indirect data register of that group. For
example, in order to write 0DH into the Framing Select Register of Channel 5 (address 0x50H>07H), one
needs to do the following:
WR
WR
The value of the indirect address register will increment after each access of the corresponding indirect data
register. Using the above example for illustration, after WRITE to the indirect data register (0x51Hex), the value
stored inside the indirect address register (0x50Hex) would become 0x08Hex. This feature can greatly
enhance the users' ability to access consecutive locations within a certain register group.
For LAPD Buffer 0 and 1 with addresses 0x06Hex and 0x07Hex respectively, there is no indirect address
register. A micro-controller WRITE access to these data registers will access the LAPD Transmit Buffers and a
micro-controller READ will access the LAPD Receive Buffers. The very first access of the LAPD buffers will
always to location 0. After each access, the pointer within the LAPD buffer will automatically increment by one,
making further access to the next location within the buffer. User should keep track of the current location
inside the buffer the READ or WRITE is associated with.
Write 0x07Hex into the indirect address register (0x50Hex) to specify address of the Framing Select
Register within the Control Register group.
Actually WRITE value 0x0DHex into the indirect data register (0x51Hex) of the Control Register group.
n_CH - n_FH
0x50
0x51
A
DDRESS
n_AH
n_BH
n_0H
n_1H
n_2H
n_3H
n_4H
n_5H
n_6H
n_7H
n_8H
n_9H
0x07
0x0D
Channel_n - Control Register Indirect Address Register
Channel_n - Control Register Indirect Data Register
Channel_n - Channel Control Indirect Address Register
Channel_n - Channel Control Indirect Data Register
Channel_n - Receive Signaling Array Indirect Address Register
Channel_n - Receive Signaling Array Indirect Data Register
Channel_n - LAPD Buffer 0 Indirect Data Register
Channel_n - LAPD Buffer 1 Indirect Data Register
Channel_n - Performance Monitor Indirect Address register
Channel_n - Performance Monitor Indirect Data register
Channel_n - Interrupt Indirect Address register
Channel_n - Interrupt Indirect Data register
Reserved
T
ABLE
8: A
54
DDRESS
M
C
AP
ONTENTS
REV. 1.0.1