XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 440

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the Receive Start of Transfer Enable bit and the Receive End of
Transfer Enable bit of the Data Link Interrupt Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
The table below shows configurations of the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
When these interrupt enable bits are set and the SLC®96 message is received in the data link channel, the
SLC®96 Data Link Controller changes the Receive Start of Transfer and Receive End of Transfer status bits of
the Data Link Status Register (DLSR). These two status indicators are valid until the Data Link Status Register
is read. Reading these register clears the associated interrupt if Reset Upon Read is selected in Interrupt
Control Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these
status indicators.
The table below shows the Receive Start of Transfer and Receive End of Transfer status bits of the Data Link
Status Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
The SLC®96 Data Link Controller can also generate interrupts when the ABORT sequence is received in the
data link channel to the microprocessor. This is the Receive ABORT Sequence (RxABORT).
To enable this interrupt, the Receive ABORT Sequence Enable bit of the Data Link Interrupt Enable Register
(DLIER) have to be set. In addition, the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register (BIER) needs to be one.
N
N
N
UMBER
UMBER
UMBER
B
B
B
5
3
3
5
3
IT
IT
IT
HDLC Controller
Receive Start of
Transfer Enable
Transfer Enable
Interrupt Enable
Receive Start of
Receive End of
Receive End of
B
B
B
Transfer
Transfer
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
RUR /
IT
IT
IT
R/W
R/W
R/W
WC
WC
T
T
T
YPE
YPE
YPE
0 - The Receive Start of Transfer interrupt is disabled.
1 - The Receive Start of Transfer interrupt is enabled.
0 - The Receive End of Transfer interrupt is disabled.
1 - The Receive End of Transfer interrupt is enabled.
0 - Every interrupt generated by the HDLC Controller is disabled.
1 - Every interrupt generated by the HDLC Controller is enabled.
0 - There is no data link message in the data link channel.
1 - The SLC®96 Data Link Controller began to receive a data link message
in the data link channel.
0 - No data link message was present in the data link channel.
1 - The SLC®96 Data Link Controller finished receiving a data link mes-
sage in the data link channel.
420
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
REV. 1.0.1