XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 65

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The Burst Access Operation will be terminated upon the rising edge of the ALE_AS input signal. At this point
the Framer will cease to internally increment the latched address value. Further, the µC/µP is now free to
execute either a Programmed I/O access or to start another Burst Access Operation with the Framer.
When an Intel-type µC/µP wishes to write data into a contiguous range of addresses, then it should do the
following.
Each of these operations within the burst access are described below.
The initial write operation of an Intel-type Write Burst Access is accomplished by executing a Programmed I/O
write cycle as summarized below.
N
b. Perform the remaining write operations, of the burst access.
b. It terminates the write cycle.
a. Perform the initial write operation of the burst access.
c. Terminate the burst access operation.
a. It latches the contents of the bi-directional data bus into the Framer Microprocessor Interface Block.
1.3.2.3.1.1.3
1.3.2.3.1.2
1.3.2.3.1.2.1
OTE
A.0
A.1
A.2
A.3
A.4
A.5
A.6
A.7
: The ALE_AS input pin should remain "Low" for the remainder of this Burst I/O Access operation.
Execute a Single Ordinary (Programmed I/O) Write cycle, as described in Steps A.1 through A.7
below.
Place the address of the initial target register (or buffer location) within the Framer, on the Address Bus
pins, A[6:0].
At the same time, the Address-Decoding circuitry (within the user's system) should assert the CS (Chip
Select) input pin of the Framer, by toggling it "Low". This step enables further communication between
the µC/µP and the Framer Microprocessor Interface block.
Assert the ALE_AS (Address Latch Enable) input pin "High". This step enables the Address Bus input
drivers, within the Microprocessor Interface Block of the Framer.
After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup
time), the µC/µP should then toggle the ALE_AS input pin "Low". This step latches the contents, on the
Address Bus pins, A[6:0], into the XRT84L38 Framer Microprocessor Interface block. At this point, the
initial address of the burst access has now been selected.
Next, the µC/µP should indicate that this current bus cycle is a Write operation by keeping the RD_DS
pin "High" and toggling the
directional data bus input drivers of the Framer.
The µC/µP places the byte (or word) that it intends to write into the target register on the bi-directional
data bus, D[7:0].
After waiting the appropriate amount of time, for the data (on the bi-directional data bus) to settle, the
µC/µP should toggle the
Write Burst Access: Intel-Mode
Terminating the Burst Access Operation
Initial Write Operation
WR_R/W
WR_R/W
(Write Strobe) input pin "High". This action accomplishes two things.
(Write Strobe) pin "Low". This action also enables the bi-
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OCTAL T1/E1/J1 FRAMER
XRT84L38