m21262 Mindspeed Technologies, m21262 Datasheet - Page 10

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m21262

Manufacturer Part Number
m21262
Description
Cdr/reclocker With 4 1 Input Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
1.1.4
The high-speed input data interface is a differential input buffer, similar to a PCML design that is referenced to
Avdd_CORE (1.2V). The high-speed serial differential data (42 Mbps to 3200 Mbps) enters the device via Din [3:0,
P/N]. Inputs 0 and 1 are internally terminated with 50Ω to VddT0/1 and inputs 2 and 3 are terminated with 50Ω to
VddT2/3. The VddT pins should be connected to AVDD_Core for a proper termination of the inputs. See
Figure 1-1
Figure 1-1.
21262-DSH-001-C
RefClkN
RefClkP
DinN
DinP
for recommended data and reference clock input coupling circuits.
Recommended Data and Reference Clock Input Coupling Circuitry
High-Speed Input/Output Pins
50Ω
50Ω
50Ω
50Ω
0.1 µF
0.1 µF
Mindspeed Proprietary and Confidential
Mindspeed Technologies
10 kΩ
2 kΩ
4.7 µF
4.7 µF
Vdd_I/O
AVdd_CORE)
(connect to
VddT
10 kΩ
2 kΩ
®
M21262
50Ω
50Ω
Reference
Clock
Input
Buffer
Data
Input
Buffer
Functional Description
2

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