m21262 Mindspeed Technologies, m21262 Datasheet - Page 56

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

3.1.9
Table 3-10.
3.1.10
Table 3-11.
21262-DSH-001-C
Bits
Bits
7:4
3:0
5:2
7
6
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Built In Self-Test (BIST) Transmitter Channel Select (BISTtx_chsel: Address 14h)
Built In Self-Test (BIST) Transmitter Main Control Register (BISTtx_ctrl: Address 15h)
Built In Self-Test (BIST) Transmitter Channel Select
Built In Self-Test (BIST) Transmitter Main Control Register
Default
Default
0000b
0000b
0000b
0b
0b
0b
1b
Reserved
tx_chan
err_insert
rx2txclk
tx_patt
en_tx
tx_rst
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Mindspeed Technologies
Label
Label
N/A
Selects which input channel the BIST Tx outputs the test pattern on
(active when BISTtx_ctrl [1] = 1).
Bit map: 1b = BIST Tx on, 0b = BIST Tx off
[3]: N/A, set to ‘0’
[2]: N/A, set to ‘0’
[1]: Input channel 1
[0]: Input channel 0
NOTE: Registers are set up to allow for multicasting BIST Tx output.
Inserts a single bit error into the PRBS Tx.
0b: Normal operation
1b: Insert error
NOTE: Setting the register high allows one error to be inserted into the
data stream. To insert another error, the user needs to clear, then set
this register bit.
Selects the source of the clock for the BIST Tx PLL (active when
BISTtx_ctrl [1] = 1).
0b: External reference frequency
1b: Recovered clock from BIST Rx
NOTE: For the recovered clock option, the BIST Rx must be enabled
with BISTrx_ctrl [1] = 1, and use the recovered clock from the same
CDR/RCLK selected by BIST Rx. This option only works for the full-rate
case.
Selects the BIST Tx test pattern (active when BISTtx_ctrl [1] = 1).
0000b: PRBS 2
0001b: PRBS 2
0010b: PRBS 2
0011b: PRBS 2
0100b: Fibre channel CJTPAT
0101b: Fibre channel CRPAT
0110b: 8b/10b countdown pattern
0111b: 16 bit user programmable pattern
1000b: 20 bit user programmable pattern
Powers up the BIST Tx and PLL.
0b: Power down
1b: Power up and enable
Resets the BIST Tx (recommended after powerup/enable; active when
BISTtx_ctrl [1] = 1).
0b: Normal BIST Tx operation
1b: Reset of BIST Tx
®
7
15
23
31
-1
-1
-1
-1
Description
Description
Registers
48