m21262 Mindspeed Technologies, m21262 Datasheet - Page 9

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1
1.1.1
Throughout this data sheet, physical pins will be denoted in bold italic print. An array of pins can be called by each
individual pin name (e.g. MF0, MF1, MF2, MF3, and MF6) or as an array (e.g. MF [6, 3:0]). The M21262 control is
accessed through registers that employ an 8-bit address and an 8-bit data scheme. Registers are denoted in italic
print, (e.g. TestRegister) and individual bits within the register will be called out as TestRegister [4:3] to denote the
4
register; if the status of the other bits are uncertain, it is recommended that the user reads the value from the
register before writing, to assure only the desired bits change. Writing in the same value to the bits within a register
does not cause glitches to the unchanged features. The addresses for the registers as well as their functions can
be found in detail in
redundant items, such as the channel number, the registers will have a nomenclature of TestReg_0 for channel 0,
TestReg_1 for channel 1, TestReg_2 for channel 2, TestReg_3 for channel 3.
1.1.2
Upon application of power, the M21262 automatically generates a master reset. At any time, forcing xRST = L
causes the M21262 to enter the master reset state. A master reset can also be initiated through the registers in the
serial interface control mode by writing AAh to Mastreset. Once a master reset is initiated, all registers are returned
to the default values, the internal state machines cleared, and all CDR/RCLK/BIST reset to the out-of-lock
condition. After a reset, the register Mastreset will automatically return to the default value of 00h.
The CDR/RCLK can be soft reset by setting CDR RCLK_ctrlA [7] = 1. The bit should be returned to 0b for normal
operation. After a soft reset, the registers that determine the CDR/RCLK operation options such as data rate,
window sizes, etc., remain unchanged and only the CDR/RCLK state machine is reset, resulting in an out-of-lock
condition.
1.1.3
The digital and analog core are designed to run at 1.2V, however, for operation from 1.8V to 3.3V, an internal linear
regulator is provided. xRegu_En = L enables the voltage regulator which uses AVdd_I/O and DVdd_I/O to
generate the required 1.2V for AVdd_Core and DVdd_Core. In this mode, the AVdd_Core and DVdd_Core pins
should be connected to a floating DC low inductance PCB plane and AC bypassed to Vss using standard
decoupling techniques. If desired, AVdd_Core and DVdd_Core can be separated into individual planes. If 1.2V is
available, it can be connected directly to AVdd_Core and DVdd_Core, to save power, by bypassing the internal
linear regulator with xRegu_En = H. In this case, it is recommended that the AVdd_Core and DVdd_Core pins be
tied together to a common PCB plane, and bypassed to Vss with standard decoupling techniques.
21262-DSH-001-C
th
and 3
rd
bit where bit 0 is the LSB and bit 7 is the MSB. Many features of the device are bit mapped within a
Detailed Feature Descriptions
Conventions
Reset
Internal Voltage Regulator
Chapter
1.0 Functional Description
3.0. The purpose of the text description is to highlight the features of the registers. For
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