m21262 Mindspeed Technologies, m21262 Datasheet - Page 27

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1.23
The BIST Rx is enabled and powered up by setting BISTrx_ctrl [1] = 1b (off by default), resetting the BIST Rx block
with BISTrx_ctrl [0] = 1b (default), and selecting a pattern with BISTrx_ctrl [5:2]. The signal to the BIST Rx is routed
from the input of the device, and the BIST Rx can only check one channel at a time. The desired channel to monitor
is selected with BISTrx_chsel [2:0]. The BIST Rx uses the recovered clock from the CDR/RCLK to drive the BIST
state machine, thus the CDR/RCLK must be enabled and locked to data for proper operation. When the data is
valid, BISTrx_ctrl [6] = 1b is used to clear the error register, and all subsequent errors can be read back through
BISTrx_error. The BIST Rx automatically synchronizes the input data with the pattern.
1.1.24
The BIST Tx is enabled and powered up by setting BISTtx_ctrl [1] = 1b (off by default), resetting the BIST Tx block
with BISTtx_ctrl [0] = 1b (default), and selecting a pattern with BISTtx_ctrl [5:2]. The high-speed clock of the BIST
Tx is generated from its own frequency multiplier PLL, that uses a selectable frequency reference determined by
BISTtx_ctrl [6]. With BISTtx_ctrl [6] = 0b (default), the external reference clock is used and typically gives the
lowest jitter output. With BISTtx_ctrl [6] = 1b the reference clock is derived from the same CDR/RCLK used to drive
the BIST Rx (this feature only works with DRD = 1 for that CDR/RCLK). In this mode, the BIST Tx output is
synchronous with the CDR/RCLK used in the BIST Rx, however, it contains the low-frequency jitter from the input
data. In either case, the BIST Tx PLL needs to be configured for the proper data rate. When the PLL is properly
configured and locked to the reference, the LOL flag should be low (BISTtx_alarm [7]). A bit error can be
intentionally inserted into the BIST Tx output, by providing a 0b, 1b, 0b sequence to BISTtx_ctrl [7].
The BIST Tx PLL setup is similar to the CDR/RCLK setup, thus, the description of similar registers for the CDR/
RCLK also applies and will not be repeated here. The desired output data rate is set with the DRD register
(BISTtx_PLL_ctrlB [3:0]) and with the VCD register (BISTtx_PLL_ctrlC [7:0]). The input reference frequency iFR is
the same as for the main CDR/RCLKs, since the same external reference and reference dividers are used. In the
internal CDR/RCLK case, iFR is F
selected by BISTrx_chsel [2:0]. Unlike the CDR/RCLK, the Tx PLL always makes iFR equal to iFV, and
BISTtx_alarm [7] is used to determine if the Tx PLL is in lock. Like the CDR/RCLKs, if the output data rate of the
BIST Tx needs to be changed, the BIST Tx requires a soft reset.
1.1.25
An internal junction temperature monitor with a range of -40°C to 130°C is integrated into the M21260. On the low
end, the temperature monitor (Tmon) is set to measure -40°C to 10°C in six 10°C steps, and on the high end, 80°C
to 130°C in six 10°C steps. The typical temperature resolution is 3°C. The temperature monitor is enabled with
Temp_mon [1] = 1b. When enabled, the temperature measurement cycle is achieved by providing a rising edge for
Temp_mon [0]. Afterwards, the correct temperature can be read from Temp_value [3:0].
mapping of the temperature to Temp_value [3:0]. Enabling and strobing the temperature in the same write cycle will
not yield reliable results.
Table 1-19.
21262-DSH-001-C
Junction Temperature Monitor (1 of 2)
Junction Temperature
BIST Receiver (BIST Rx) Operation
BIST Transmitter (BIST Tx) Operation
Junction Temperature Monitor
130°C > Tc ≥ 120°C
120°C > Tc ≥ 110°C
110°C > Tc ≥ 100°C
100°C > Tc ≥ 90°C
Tc ≥ 130°C
vco, rxRCLK
Mindspeed Proprietary and Confidential
Mindspeed Technologies
/128, where F
vco, rxRCLK
Temp_value [3:0]
1100b
1011b
1010b
1001b
1000b
®
is the VCO frequency of the CDR/RCLK
Functional Description
Table 1-19
High-warning
Condition
High-alarm
High-alarm
Normal
Normal
shows the
19