m21262 Mindspeed Technologies, m21262 Datasheet - Page 21

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1.16
For multirate operation, the first step is to determine the desired data rate range. The input data range must be
bracketed by DF
data rate frequencies, DRD
F
valid data rates are shown in
Table 1-11.
It is important to note the difference between the VCO frequency (F
always between 2 GHz to 3.2 GHz, while DF is the divided down F
1.1.17
Frequency acquisition is enabled by the LOLCir when LOL = H (Alarm_LOL = H or xLOL = L). A secondary FLL
attempts to lock the VCO to a frequency derived from the external reference. When the frequency is close to the
desired frequency, LOLCir sets LOL = L and disables the secondary FLL, thus, the main CDR/RCLK PLL is free to
phase lock to the incoming data. Although the main CDR/RCLK PLL can achieve frequency lock, the VCO
frequency tuning range typically exceeds the CDR/RCLK PLL inherent acquisition range. This implies that the FLL
needs to get the VCO within the CDR/RCLK PLL range. The loss of lock circuitry (LOLCir) is used to determine
when the secondary FLL is active. The LOLCir consists of window detectors that constantly compare a scaled VCO
frequency, to a frequency related to the external reference. When LOL = H the loop is out of lock, the FLL is
activated until the frequency difference is within the narrow reference window (NRW). When LOL = L, the FLL is
not engaged until the frequency exceeds the wide reference window (WRW). If a signal is not present, the FLL
circuit will drive the VCO frequency to the NRW and turn off. Without data present, the VCO would then drift until
the frequency difference exceeds the WRW, and repeat this cycle. To prevent this, by default, the FLL is activated
with LOL = H and de-activated with LOL = L.
21262-DSH-001-C
Data rate divider (DRD = 1): CDR_ctrlB [3:0] = 0000b
Data rate divider (DRD = 2): CDR_ctrlB [3:0] = 0001b
Data rate divider (DRD = 4): CDR_ctrlB [3:0] = 0010b
Data rate divider (DRD = 8): CDR_ctrlB [3:0] = 0011b
Data rate divider (DRD = 12): CDR_ctrlB [3:0] = 0100b
Data rate divider (DRD = 16): CDR_ctrlB [3:0] = 0101b
Data rate divider (DRD = 24): CDR_ctrlB [3:0] = 0110b
Data rate divider (DRD = 32): CDR_ctrlB [3:0] = 0111b
Data rate divider (DRD = 48): CDR_ctrlB [3:0] = 1000b
vco, min
/F
vco, max
Valid Input Data Ranges
min
are the minimum/maximum VCO frequencies, which are 2.0 GHz and 3.2 GHz respectively. The
Multirate CDR Data Rate Selection
Frequency Acquisition
= F
vco, min
max/min
Parameter
Table
/DRD
are the maximum/minimum data rate divider settings using CDR_ctrlB [3:0], and
1-11.
max
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to DF
max
= F
vco, max
/DRD
min
vco
®
vco
. DF
that matches the input data rate.
), and the data rate frequency (DF). F
max/min
DF
166.7
83.33
62.5
500
250
125
2.0
1.0
42
min
are the maximum/minimum input
Functional Description
DF
266.66
133.33
66.66
800
400
200
100
3.2
1.6
max
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
GHz
GHz
vco
is
13