m21262 Mindspeed Technologies, m21262 Datasheet - Page 15

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Figure 1-3.
Figure 1-4
edge of SCLK, the 10-bits consisting of SB = 1, OP = 1, and the 8-bit ADDR are written to the serial input shift
register and copied to the serial output shift register. On the next rising edge after the address LSB, the SB and
8-bits of the DATA are shifted out. The SB for a Read is always 0.
Figure 1-4.
On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 16-bits following SB
and OP are used. On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or
OP renders the operation undefined. The falling edge of xCS always resets the serial operation for a new Read or
Write cycle.
The timing diagrams for the serial write and read operations are shown in
Table 1-8
21262-DSH-001-C
SCLK
SCLK
xC S
SDI
SD O
xCS
SD I
Tens
contains the specifications for the various timing parameters for the serial programming interface.
Tens
illustrates the Serial Read mode in where xCS goes low before the falling edge of SCLK. On each falling
Serial WRITE Mode
Serial READ Mode
1
1
r d
w r
T
a 7
T
a 7
dw
dw
a 6
T
a 6
ds
a 5
T
a 5
ds
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a 4
a 4
T
dh
a 3
a 2
T
dh
a1
T
clk
a1
a0
a 0
X
0
T
wclk
®
d7
d 7
X
d 6
Figure 1-3
d6
X
T
wclk
d5
d 5
X
d4
T
d 4
X
clk
and
T
Functional Description
rdd
d 3
d 3
X
Figure
d 2
T
d 2
X
rds
1-4, respectively.
d 1
d 1
X
T
T
cs
cs
d0
d0
X
T
T
1
ch
1
ch
7