m21262 Mindspeed Technologies, m21262 Datasheet - Page 50

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Figure 2-14. Trace Length Matching Using Serpentine Pattern
Figure 2-15. Loop Length Matching for Differential Traces
The loop length matching method shown in
create a large impedance discontinuity in the transmission line, which could result in higher jitter on the signal and/
or a greater sensitivity to noise for the differential pair.
When using capacitors to AC-couple the input, care should be taken to minimize the pattern-dependant jitter (PD
associated with the low-frequency cutoff of the coupling network. When NRZ data containing long strings of 1s or
0s is applied to a high-pass filter, a voltage droop occurs. This voltage droop causes PD
as inter-symbol interference (ISI) is generated from dispersion effects of long trace lengths in backplane material.
If needed, use 0.1 µ F capacitors to AC-couple the high-speed output signals, and the reference clock inputs. The
high-speed data input signals can be DC-coupled.
On the Evaluation Module (EVM), we have tied DVdd_I/O and AVdd_I/O together to minimize the number of power
supply jacks. They are kept separate on-chip to give the flexibility to the system designers to supply a different
voltage level for each. For instance, an FPGA can be used to supply power to DVdd_I/O, while a lower voltage can
be used to power AVdd_I/O to minimize power dissipation. On the EVM, we have also tied DVdd_Core and
AVdd_Core together to minimize the number of power supply jacks. They are kept separate on-chip to provide
more isolation, however, if the system board plane is properly decoupled, they can be tied together.
No inductive filtering on the system board is necessary between different power supplies of the IC. It is up to the
system designer to determine if this needs to be considered for supplies that are coming from other parts of the
system board (such as switching regulators or ASICs).
An inductor should not be used at the VddT pins. These pins were made available to create a low AC impedance,
such that the 50
and differential termination. If common-mode termination is not important (such as in LVDS applications), simply
leave the VddT pins floating. Note that a low AC impedance can also be created by tying the VddT pins to the
AVdd_I/O plane, thus saving on the number of external capacitors. This, however, implies a CML-like data interface
(unless the data is AC-coupled). VddT is not really a supply plane on-chip, it is simply the point to which the 50
input impedances are tied.
Power planes should be decoupled to ground planes using thin dielectric layers, to increase capacitance
(preferably 2–4 mils). Reference ground layers should be used on both sides of inner layer routing planes, with
controlled impedance. The total board thickness should meet the standard drill holes to board thickness ratio of
1:12 or 1:14.
21262-DSH-001-C
Ω
on-chip termination impedances see a common AC ground. This assures both common-mode
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Figure 2-15
will match the trace lengths of a differential pair, but will
®
J
Product Specifications
in much the same fashion
Ω
J
42
)