m21262 Mindspeed Technologies, m21262 Datasheet - Page 14

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1.9
The second serial interface mode is a four-wire programming interface that has been traditionally used on MSPD
earlier generation crosspoints and CDRs and is capable of higher speed operation then the two-wire interface. The
interface consists of a unidirectional clock and a data input and data output line. For use with multiple ICs, a serial
interface chip select pin is provided.
multifunction pins. This serial interface can operate with a maximum clock rate of 20 MHz.
Table 1-7.
The serial I/O shifts data in from the external controller on the rising edge of SCLK. The serial I/O operation is
gated by xCS. Data is shifted in on SDI on the falling edge of SCLK, and shifted out on SDO on the rising edge of
SCLK. To address a register, a 10-bit input consists of the first bit (Start Bit, SB = 1), the second bit (Operation Bit,
OP = 1 for read, = 0 for write), followed by the 8-bit ADDR (MSB first) as shown in
Figure 1-2.
Figure 1-3
SCLK. On each falling edge of the clock, the 18-bits consisting of the SB = 1, OP = 0, ADDR, and DATA, are
latched into the input shift register. The rising edge of xCS must occur before the falling edge of SCLK for the last
bit. Upon receipt of the last bit, one additional cycle of SCLK is necessary before DATA transfers from the input shift
register to the addressed register. If consecutive read/write cycles are being performed, it is not necessary to insert
an extra clock cycle between read/write cycles, however one extra clock cycle is needed after the last data bit of the
last read/write cycle.
21262-DSH-001-C
MF10
MF11
MF4
MF5
Pin
illustrates the Serial Write Mode. To initiate a Write sequence, xCS goes low before the falling edge of
Multifunction Pins for Four-Wire Interface
Serial Word Format
Start Bit
Multifunction Pins: Four-Wire Serial Interface
Function
SCLK
17 16
SDO
1
xCS
SDI
rw
MSB
Read/Write
15
Table 1-7
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Address
Serial Data In
Chip Select, active low
Clock
Serial Data Out
A[7:0]
illustrates how the four-wire serial interface maps into the
LSB
8
MSB
7
®
Description
D[7:0]
Data
Figure
Functional Description
1-2.
LSB
0
6