m21262 Mindspeed Technologies, m21262 Datasheet - Page 22

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Figure 1-8.
Figure 1-8
version of the internal VCO frequency (iFV) with a scaled version of the reference clock frequency (iFR); iFR and
iFV are limited to between 10 MHz and 25 MHz. The external reference clock frequency (F
RefClk [P/N] terminals. This reference frequency is scaled to the iFR by the reference frequency divider (RFD)
[Refclk_ctrl [3:1]], which allows for an external reference clock in the range of 10 MHz to 800 MHz. The RFD level is
a globally set value that applies to all CDR/RCLKs.
maximum F
Table 1-12.
The VCO frequency is scaled to the iFV by the VCO comparison divider (VCD) [RCLK_ctrlC_N [7:0]].
provides DRD, RFD, and VCD values for common applications.
data rates, a 19.44 MHz reference clock frequency must be used. For applications where a combination of
SONET/SDH and other data rates are used, a 25 MHz reference clock frequency must be used. If either of
these reference clock frequencies is not available, please contact Mindspeed Technologies Applications
Engineering for other options.
21262-DSH-001-C
RFD (Refclk_ctrl [3:1] = 000b): divide by 1
RFD (Refclk_ctrl [3:1] = 001b): divide by 2
RFD (Refclk_ctrl [3:1] = 010b): divide by 4
RFD (Refclk_ctrl [3:1] = 011b): divide by 8
RFD (Refclk_ctrl [3:1] = 100b): divide by 12
RFD (Refclk_ctrl [3:1] = 101b): divide by 16
RFD (Refclk_ctrl [3:1] = 110b): divide by 32
D
F
vco,max
in
RefClk
shows a block diagram of the frequency acquisition circuits. The secondary FLL compares a scaled
ref
values.
Block Diagram of Frequency Acquisition Circuits
Reference Clock Frequency Ranges
> F
VCO
vco
RFD Value
> F
vco,min
F
ref
LOL
F
vco
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LOLCir
CDR_ctrlB [3:0]
CDR_ctrlC [7:0]
Refclk_ctrl [3:1]
Table 1-12
DRD
VCD
RFD
Minimum F
gives the divider ratio, along with the minimum and
For applications that only deal with SONET/SDH
120
160
320
10
20
40
80
®
iFV
iFR
DR
F
ref
CLK
(MHz)
LOA
D
D
D
C
1
2
in
in
FLL
CDR
Functional Description
Error
Error
D
C
Maximum F
ref
out
out
) is applied to the
100
200
300
400
800
25
50
ref
D
C
Table 1-13
(MHz)
out
out
14