m21262 Mindspeed Technologies, m21262 Datasheet - Page 52

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Table 3-1.
21262-DSH-001-C
Addr
1Dh
00h
01h
04h
05h
06h
07h
11h
12h
14h
15h
17h
18h
19h
1Ah
1Bh
1Ch
1Fh
20h
21h
30h
31h
40h
41h
42h
43h
44h
45h
46h
49h
4Ah
Register Name
BISTtx_PLL_ctrlA
BISTtx_PLL_ctrlB
BISTtx_PLL_ctrlC
BISTtx_LOLctrl
BIST_pattern0
BIST_pattern1
BIST_pattern2
BISTtx_alarm
BISTrx_error
BISTtx_chsel
Preemp_ctrl
Temp_value
Temp_mon
Alarm_LOL
Alarm_LOA
RCLK_ctrlA
RCLK_ctrlB
RCLK_ctrlC
Refclk_ctrl
BISTrx_ctrl
BISTtx_ctrl
Phadj_ctrl
Mastreset
Chipcode
Jitter_red
mux_ctrl
Revcode
Ineq_ctrl
LOL_ctrl
Out_ctrl
Globctrl
Register Table Summary
RCLKmode[1]
PLLmode[1]
chipcode[7]
VCO_divr[7]
VCO_divr[7]
pattern[15]
revcode[7]
d7: MSB
pattern[7]
MSPD int
err_insert
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
i_trim[1]
powerup
port3[1]
reserved
reserved
softreset
softreset
outlvl[1]
reserved
reserved
tx_LOL
err[7]
rst
—
—
—
3.0 Registers
RCLKmode[0]
PLLmode[0]
VCO_divr[6]
VCO_divr[6]
chipcode[6]
pattern[14]
revcode[6]
pattern[6]
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
reserved
reserved
reserved
i_trim[0]
port3[0]
rx_ctrclr
outlvl[0]
rx2txclk
err[6]
d6
rst
—
—
—
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tacq_LOL[0]
tacq_LOL[0]
VCO_divr[5]
VCO_divr[5]
chipcode[5]
pattern[13]
revcode[5]
pattern[5]
MSPD int
MSPD int
tx_patt[3]
MSPD int
MSPD int
MSPD int
inh_force
MSPD int
MSPD int
MSPD int
MSPD int
reserved
reserved
reserved
reserved
reserved
port2[1]
r_sel[1]
err[5]
d5
Common Registers
rst
—
—
—
chipcode[4]
VCO_divr[4]
VCO_divr[4]
en_DCservo
pattern[12]
revcode[4]
pattern[4]
MSPD int
MSPD int
tx_patt[2]
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
port2[0]
reserved
reserved
reserved
reserved
r_sel[0]
err[4]
d4
rst
—
—
—
®
data_pol_flip
phase_adj[3]
VCO_divr[3]
VCO_divr[3]
chipcode[3]
data_rate[3]
data_rate[3]
revcode[3]
pattern[19]
pattern[11]
autoinh_en
ref_divr[2]
tx_patt[1]
pattern[3]
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
port1[1]
reserved
reserved
temp[3]
err[3]
d3
rst
phase_adj[2]
data_rate[2]
VCO_divr[2]
data_rate[2]
VCO_divr[2]
chipcode[2]
preemph[2]
pattern[18]
pattern[10]
dataout_en
ref_divr[1]
revcode[2]
rx_patt[0]
MSPD int
MSPD int
tx_patt[0]
MSPD int
MSPD int
pattern[2]
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
reserved
in_eq[2]
port1[0]
temp[2]
err[2]
d2
rst
narwin_LOL[0]
narwin_LOL[0]
en_temp_mon
phase_adj[1]
VCO_divr[1]
VCO_divr[1]
chipcode[1]
data_rate[1]
data_rate[1]
preemph[1]
revcode[1]
pattern[17]
ref_divr[0]
pattern[9]
pattern[1]
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
reserved
port0[1]
reserved
in_eq[1]
temp[1]
LOA_en
en_rx
err[1]
en_tx
d1
rst
widwin_LOL[0]
widwin_LOL[0]
phase_adj[0]
VCO_divr[0]
strobe_temp
VCO_divr[0]
chipcode[0]
data_rate[0]
data_rate[0]
preemph[0]
revcode[0]
pattern[16]
tx_chan_0
clear_alm
pattern[8]
pattern[0]
d0: LSB
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
port0[0]
in_eq[0]
temp[0]
rx_rst
err[0]
tx_rst
LOL
LOA
rst
44