m21262 Mindspeed Technologies, m21262 Datasheet - Page 19

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1.13
The output channel contains an output pre-emphasis circuit that can be used to select the optimal pre-emphasis
level. The pre-emphasis settings have been optimized for a variety of backplane PCB applications. For board
traces on FR4, the pre-emphasis circuit can drive trace lengths up to 60” at 1.6 Gbps. Like the input equalizer
settings, the output pre-emphasis circuit has similar high performance on Nelco-13, Arlon 25, Rogers 3003, 4003C,
4340, GeTek PCB materials, and twinaxial cables. The digital pre-emphasis level is selected, for each output
channel, with Preemp_ctrl [2:0], and the default value of 000b corresponds to pre-emphasis disabled. The pre-
emphasis circuit tracks the signal data rate throughout the multirate range, however, like the input equalizer, it is
designed to compensate for the bandwidth limitations of the interconnect, and may not have the desired effects at
the low end of the multirate range. When the CDR/RCLK has been disabled or bypassed, analog pre-emphasis
must be used in place of digital pre-emphasis. Writing the data value 1b to the register Preemp_ctrl [3] enables
analog pre-emphasis, whereas writing the data value 0b to the register Preemp_ctrl [3] enables digital pre-
emphasis. Once analog pre-emphasis has been enabled, the boost level may be chosen with Preemp_ctrl [5:4],
and the bandwidth may be chosen with Preemp_ctrl [6]. The output pre-emphasis function is available for all data
interfaces and levels.
Figure 1-7.
1.1.14
When the CDR/RCLK achieves phase lock onto the incoming data stream, it removes the incoming random jitter
above its loop bandwidth. The M21262 output data has extremely low jitter, due to retiming with a very low jitter
generation CDR/RCLK. Clock outputs are also provided, but are disabled by default.
Each CDR/RCLK is capable of multirate operation which is achieved by a combination of built in VCO frequency
dividers (VCD), Data Rate Dividers (DRD), and a wide VCO tuning range (F
result, the allowed input data range is F
ranges are deliberately chosen to cover all typical applications.
By default, the loop bandwidth is set to pass 2 x HD-SDI Video and SONET STS-48 specifications, with less than
0.1 dB of bandwidth peaking. Within a given VCO frequency range, the bandwidth will scale proportionately. For
example, if the loop bandwidth (LBW) is 1.19 MHz at 1.485 GHz, then at 2.97 GHz the LBW will be 2.38 MHz, and
21262-DSH-001-C
Definition of Pre-Emphasis Levels
Output Pre-Emphasis
CDR/RCLK Overview
Pre-Empasis Level =
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min
/ DRD
max
to F
max
/ DRD
V
V
min
B
®
S
. Although the ranges are not continuous, the
V
V
B
S
x 100
min =
2.0 GHz, F
Functional Description
max
= 3.2 GHz). As a
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