m21262 Mindspeed Technologies, m21262 Datasheet - Page 25

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

1.1.19
Table 1-16
is required to center the VCO.
Table 1-16.
F
DRD is the data rate divider (1, 2, 4, 8, 12, 16, 24, 32, 48) set with rclk_ctrlB_N[3:0]. T
supported, which decreases for F
to 4; to lock to this signal the VCO needs to operate at 3.2 GHz. Under these conditions the ambient temperature
range supported is 0°C–70°C, and it is necessary to center the VCO in each of the four lanes.
The VCO tuning range is roughly the same bandwidth as the variation in VCO center frequency between the
extremes of the operating temperature range. This issue can be resolved by centering the VCO frequency during
the in-circuit testing (ICT) phase prior to shipment of the customer systems.
NOTE: The CDR/RCLK must be powered up and configured at 25°C–40°C ambient temperature during ICT.
1. Power up the device and configure the registers via the serial interface with the appropriate settings for the
2. Read and store the VCO trim code from register MBh[4:0].
3. Every time the device is powered up, this trim code must be forced by setting M0h[0] = 0b then writing the code
It should be noted that it is not possible to center the VCO in the hardwired mode, it is necessary to program the
CDR/RCLK using the serial interface.
1.1.20
By default, the LOA detector is enabled and can be disabled by setting CDR_ctrlA_N [1] = 0b, where N is the
channel number. Loss of activity measures the transition density of data to determine if the data is valid. With
PRBS data, the transition density is typically 50%, averaged over long periods. During small time intervals, data
transition density variations are due to data content, packet headers, stress patterns, etc. In some applications,
when data is not present, noise produces rail-to-rail transitions that cause problems with level based detectors.
These applications include cascaded reclockers, high-gain crosspoints, and other devices. The data transition
density based LOA detector can separate data from random noise, determine false lock at the wrong integer and
non-integer data rate, signal stuck high/low conditions, and determine false lock to retimed noise. Unlike level
based detectors, it cannot determine false lock with low amplitude data.
1.1.21
The M21262 contains a BIST test pattern generator as well as a test pattern receiver. Both the BIST transmitter
(BIST Tx), and BIST receiver (BIST Rx) are designed to operate with fixed patterns. For PRBS evaluation, the
PRBS 2
21262-DSH-001-C
VCO
application of interest.
to MAh[4:0]. This can be done during the same write cycle as when the other registers are configured.
F
2.0–2.666
VCO
is the VCO frequency, which always lies in the range 2.0–3.2 GHz. DR is the data rate of the input signal, and
2.7–2.97
2.7–2.97
3.0–3.2
7
-1, 2
(GHz)
summarizes the supported ambient temperature range as a function of data rate, and indicates when it
15
Supported Ambient Temperature Range by Data Rate
-1, 2
Ambient Temperature Range Limitations
Loss of Activity
Built-In Self Test (BIST) Overview
23
-1, and 2
2.0/DRD–2.666/DRD
2.7/DRD–2.97/DRD
2.7/DRD–2.97/DRD
3.0/DRD–3.2/DRD
DR (Gbps)
31
-1 test patterns are provided. For 8b/10b testing, the fibre channel CRPAT and
VCO
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> 2.666 GHz. As an example, if the data rate is 800 Mbps DRD should be set
T
-40–85
-40–85
a
0–70
0–70
(°C)
®
VCO Centering Requirement
a
is the ambient temperature
Functional Description
N
N
Y
Y
17